Chiplet Interconnect Market Intelligence: Size, Share and Growth Outlook Through 2035

Market Overview

Market size and scope

• Brevintel analysis values the chiplet interconnect market at USD 2.17 billion in 2025 ($2.17B), projected to reach USD 2.89 billion in 2026 and USD 41.2 billion by 2035 ($41.2B), expanding at a CAGR of approximately 34.36% during 2026-2035.
• Coverage spans electrical and optical die-to-die links, SerDes and parallel signaling, open and proprietary protocol models, PHY and controller/protocol IP, plus silicon interposers, embedded bridges, and organic or fan-out RDL platforms.
• Intel Corporation led with over 18.2% market share in 2025; the top five—Intel, Advanced Micro Devices (AMD), NVIDIA Corporation, TSMC, and Samsung Electronics—collectively held 56.3%.
• Chiplet designs let compute, I/O, memory, analog, and accelerator functions use different process nodes instead of one monolithic die.
• AMD's fourth-generation EPYC architecture connects up to 12 5nm Zen 4 compute dies to an I/O die through GMI3 links operating at 32 Gbps, keeping I/O on a more economical node.
• Each disaggregated design creates die-to-die requirements spanning physical signaling, protocol control, package routing, validation, and thermal co-design.
• UCIe was formed in 2022 by 12 founding board members spanning AMD, Intel, NVIDIA, Qualcomm, Samsung, TSMC, Arm, Google Cloud, Meta, Microsoft, Alibaba, and ASE.
• Specifications expanded from 2D and 2.5D die-to-die I/O in UCIe 1.x to 3D packaging support in UCIe 2.0 and 64 GT/s capability in UCIe 3.0, released in August 2025.

Demand context and policy backdrop

• AI accelerators and HPC systems are the principal near-term demand centers because performance depends on moving data among compute tiles and high-bandwidth memory inside tightly integrated packages.
• The National Advanced Packaging Manufacturing Program supports advanced substrates, photonics, thermal management, chiplets, and co-design.
• The U.S. Department of Commerce announced up to USD 1.6 billion in NAPMP R&D funding across five advanced-packaging technology areas.
• DARPA's NGMM program treats 3D heterogeneous integration as foundational to defense and commercial microelectronics manufacturing.
• Brevintel analysis indicates the 34.36% CAGR through 2035 reflects a structural redesign of semiconductor value creation rather than a short-lived accelerator cycle.
• The economic advantage is reserving leading-edge wafer capacity for compute tiles while assigning I/O, analog, and less density-sensitive functions to mature nodes.
• Intel's EMIB connects adjacent chiplets at a 45 µm bump pitch, while Foveros Direct supports face-to-face copper bonding at a 9 µm pitch.
• Intel's objective of reaching one trillion transistors per package by 2030 underscores why higher-density packaging is central to interconnect demand.

Market Dynamics

Key drivers

• Heterogeneous integration lets designers combine functions with different node, performance, and reliability requirements inside one package.
• Intel's second-generation EMIB reduces bump pitch from 55 µm to 45 µm, raising density for horizontally adjacent chiplets.
• Advanced-node cost optimization shifts spend toward die-to-die PHY, protocol, package routing, and co-design tools as functional disaggregation rises.
• AI and HPC workload scaling make package-level bandwidth a determinant of usable system performance between compute tiles and HBM.
• NIST states recent AI advances would not have been possible without advanced packaging, and NAPMP includes photonics and RF connector technology among five R&D areas.
• Yield improvement and design flexibility arise when compute, cache, I/O, and specialized accelerators are optimized independently before final assembly.
• Intel's Foveros 2.5D approach uses a passive base die with face-to-face active dies to combine functions from different nodes in one package.
• UCIe reduces the cost of joining a multi-vendor chiplet ecosystem by defining common physical, protocol, and software-stack elements; UCIe 2.0 added UCIe-3D support, a DFx manageability architecture, and compliance-testing frameworks.

Key restraints

• Incomplete interoperability remains a constraint: UCIe 2.0 introduced compliance frameworks and stated that interoperability among different PHY vendors had not yet been validated at scale.
• Designers must still qualify PHY implementations, protocol controllers, package substrates, power-delivery networks, and system-management features together.
• Large integrated companies can optimize proprietary fabrics around their own products, while smaller designers face higher verification overhead across foundry boundaries.
• Thermal and power management intensify as finer-pitch interconnects and denser stacking raise heat-management burden inside the package.
• Intel identifies thermal warping as a challenge that EMIB and Foveros hybrid packaging approaches must address through structural engineering.
• NAPMP separately lists power delivery and thermal management as a priority R&D area, indicating these constraints remain material at the industry level.
• Brevintel analysis finds interoperability is largely an ecosystem and business-model problem that compliance programs and qualified IP can ease over 2026-2030.
• Thermal management does not improve passively as standards proliferate because more dies, tighter pitch, and greater bandwidth density intensify thermal gradients and mechanical stress.

Segmentation Analysis

By interconnect type

• Electrical interconnects accounted for USD 1,344.81 million in 2025 (USD 1.34 billion) and are projected to reach USD 1,777.52 million in 2026 and USD 23,648.93 million by 2035, growing at a CAGR of 33.32%.
• Electrical scale reflects copper micro-bumps, redistribution layers, through-silicon vias, and short-reach electrical links used in processor, accelerator, and HBM-integrated packages.
• Optical interconnects are projected to rise from USD 822.82 million in 2025 to USD 1,109.94 million in 2026 and USD 17,551.29 million by 2035, at a CAGR of 35.90%.
• Ayar Labs announced TeraPHY in March 2025 as an 8 Tbps UCIe-compliant optical I/O chiplet bridging chiplet-scale electrical connectivity and photonic transmission.
• TeraPHY integration with SuperNova remote light sources has been demonstrated in an arrangement supporting up to one petabit per second of bidirectional bandwidth.
• Slower electrical growth versus optical does not imply displacement in core package routing; optical rises where reach, aggregate bandwidth, and energy constraints exceed copper limits.
• Brevintel analysis treats electrical links as the installed base for short, high-density connections and optical as the system-scaling layer beyond the package.
• NAPMP's connector-technology focus, including photonics, further supports optical chiplet adoption in AI scale-up fabrics.

By signaling architecture

• SerDes-based interconnects generated USD 1,182.35 million in 2025 (USD 1.18 billion) and are expected to reach USD 19,611.30 million by 2035, expanding at a CAGR of 32.54%.
• SerDes remains important for high-speed serial links, socket-level communication, and longer-reach I/O; AMD's EPYC architecture employs PCIe Gen 5 SerDes for external and socket connectivity.
• Parallel-based architectures are projected to expand from USD 985.28 million in 2025 to USD 21,588.92 million by 2035, at a segment-leading architecture CAGR of 36.25%.
• UCIe is designed around short-reach die-to-die I/O for standard and advanced packages, fitting silicon interposer and embedded-bridge layouts.
• Many high-density die-to-die connections occur over extremely short distances on interposers and bridges, favoring wide parallel interfaces over serial power and complexity trade-offs.
• As packages integrate more compute tiles and HBM stacks, qualified parallel interfaces tied to specific package technologies and foundry design environments gain commercial priority.
• Brevintel analysis links parallel signaling growth directly to the same package-density trends that drive AI accelerators.
• Architecture choice increasingly depends on package context rather than a generic high-speed link specification alone.

By protocol model

• Open-standard protocols are projected to grow from USD 847.34 million in 2025 to USD 19,116.90 million by 2035, at the highest CAGR across segmentation dimensions, 36.68%.
• UCIe provides the strongest ecosystem reference point, with more than 130 member companies and a trajectory that includes 3D packaging support, manageability, compliance testing, and 64 GT/s performance.
• Proprietary die-to-die protocols represented USD 1,320.29 million in 2025 (USD 1.32 billion) and are projected to reach USD 22,083.32 million by 2035, at a CAGR of 32.63%.
• The larger proprietary 2025 base reflects installed architectures of major processor and accelerator suppliers optimizing bandwidth, latency, and coherency.
• AMD's GMI3 links in EPYC exemplify a proprietary interconnect optimized within a broader product architecture.
• Open protocols are particularly relevant where customers seek reusable IP, multi-vendor sourcing, or foundry-portable design flows.
• Proprietary protocols remain important for leading-edge integrated systems where differentiation depends on tightly coupled hardware and software.
• Brevintel analysis expects open-standard growth premiums to reflect lower integration and verification risk once interoperability is proven in silicon and package environments.

By interconnect IP layer

• PHY IP is projected to rise from USD 1,313.64 million in 2025 to USD 22,660.12 million in 2035, at a CAGR of 33.06%, covering electrical signal conditioning, calibration, clocking, data recovery, and optical electro-conversion.
• PHY capability is mandatory in every chiplet connection, which explains its large revenue base and package-context sensitivity across bump pitch, substrate, channel loss, and thermal envelope.
• Controller and protocol IP is projected to increase from USD 853.99 million in 2025 to USD 18,540.10 million by 2035, at a CAGR of 36.13%.
• Controller and protocol IP includes link control, protocol adaptation, manageability, coherency, and flow-control functions required for multi-die system behavior.
• UCIe 2.0's DFx architecture demonstrates growing importance of manageability and lifecycle visibility in multi-chiplet systems.
• The higher controller/protocol CAGR versus PHY indicates system complexity is migrating upward as packages incorporate more heterogeneous dies.
• Suppliers compete on process portability, package-aware modeling, and verification support in addition to raw signal performance.
• Brevintel analysis favors vendors that pair validated PHY with controller IP and integration collateral across foundry PDKs.

By interconnect-enabling hardware

• Silicon interposers are projected to grow from USD 1,024.93 million in 2025 to USD 19,776.11 million by 2035, at a CAGR of 34.56%, providing dense routing for compute, memory, and I/O tiles.
• Embedded silicon bridges are projected to grow from USD 788.28 million in 2025 to USD 17,468.89 million by 2035, at a CAGR of 36.44%, reflecting EMIB-style localized high-density connectivity without a full-area interposer.
• Organic interposers and fan-out RDL are projected to increase from USD 354.42 million in 2025 to USD 3,955.22 million by 2035, at a CAGR of 27.20%.
• NIST awarded funding to Arizona State University for 300 mm wafer-level and 600 mm panel-level fan-out packaging development under the NAPMP program.
• Intel positions EMIB as high-bandwidth connectivity between large chiplets without a full silicon interposer, confirming the interposer as a benchmark high-density architecture.
• Bridge-based architectures balance package density with material cost and thermal design where full interposers add unnecessary area.
• Organic and fan-out platforms retain roles in automotive, industrial, consumer, and other cost-sensitive applications.
• Brevintel analysis sees hardware mix shifting toward localized density where AI packages demand extreme bandwidth without uniform full-area silicon cost.

By end use

• HPC is projected to grow from USD 313.48 million in 2025 to USD 5,438.43 million by 2035, at approximately 33.14%, supported by scientific, defense, and large-scale modeling workloads.
• AI/ML accelerators are the fastest-growing end-use segment, rising from USD 423.60 million in 2025 to USD 9,888.05 million by 2035, at approximately 37.15%.
• Data center and cloud infrastructure is projected to expand from USD 439.61 million in 2025 to USD 8,652.05 million by 2035, at approximately 34.83%.
• Networking and switching ASICs are projected to rise from USD 287.96 million in 2025 to USD 5,356.03 million by 2035, at approximately 34.07%.
• Automotive electronics demand is projected to grow from USD 230.02 million in 2025 to USD 3,996.42 million by 2035, at approximately 33.16%; UCIe 1.1 added automotive reliability and cost-optimized packaging extensions.
• Consumer computing is expected to increase from USD 179.78 million in 2025 to USD 3,213.62 million by 2035, at approximately 33.54%.
• Industrial and edge computing is projected to expand from USD 154.57 million in 2025 to USD 2,678.01 million by 2035, at approximately 33.12%.
• Other applications, including medical electronics, communications infrastructure, and aerospace-related systems, are projected to grow from USD 138.61 million in 2025 to USD 1,977.61 million by 2035, at approximately 30.38%.

Regional Outlook

North America

• North America led with a 42.7% share in 2025, held USD 924.57 million in 2025, and is projected to reach USD 1,232.72 million in 2026, advancing at a CAGR of 34.48%.
• The region captures substantial value in fabless chiplet design, proprietary processor architectures, PHY and protocol IP, EDA software, and optical-interconnect development.
• Public investment includes up to USD 1.6 billion in NAPMP R&D funding across equipment, thermal management, connector technology, chiplets, and co-design.
• NIST's USD 300 million advanced-packaging awards to Absolics, Applied Materials, and Arizona State University aim to strengthen domestic substrate and fan-out packaging capabilities.
• DARPA's NGMM program further supports 3D heterogeneous integration R&D and pilot-production infrastructure.
• Intel's EMIB and Foveros platforms, AMD's chiplet processor architectures, and Ayar Labs' optical I/O development concentrate interconnect innovation in the region.
• Canada contributes through high-speed connectivity and IP expertise, including Alphawave Semi's die-to-die and SerDes-oriented capabilities.
• Brevintel analysis notes high-value design activity remains materially dependent on advanced packaging capacity located in Asia for volume AI accelerator production.

Europe

• Europe generated USD 382.89 million in 2025 and is projected to reach USD 502.84 million in 2026, at a CAGR of 32.46%.
• Regional role is weighted toward EDA, mixed-signal and connectivity IP, automotive semiconductor design, industrial electronics, and advanced research.
• Automotive and industrial demand provide a durable application base with long qualification cycles and heterogeneous integration of processing, sensing, connectivity, and power management.
• UCIe 1.1's automotive reliability extensions are especially relevant to European use cases.
• Europe's growth rate remains below North America and Asia Pacific because the region lacks advanced packaging manufacturing capacity at comparable scale.
• Brevintel analysis highlights the limits of a strong downstream technology base without comparable advanced-packaging scale.
• The region can benefit from automotive, industrial, and design-tool demand without commanding the same manufacturing leverage over high-density AI packages.
• Qualification-sensitive programs remain the primary European commercial pathway through 2035.

Asia Pacific

• Asia Pacific held USD 704.83 million in 2025 and is projected to reach USD 949.74 million in 2026, recording the fastest regional CAGR at 35.91%.
• Regional lead rests on advanced foundry processes, silicon interposers, HBM supply, OSAT capacity, and high-volume package production across Taiwan, South Korea, Japan, Malaysia, Vietnam, and other manufacturing locations.
• Taiwan is central through TSMC's advanced packaging operations and its role as a UCIe founding member.
• South Korea contributes through Samsung's foundry, advanced packaging, and memory capabilities, while Japan provides a growing base for advanced semiconductor manufacturing and materials development.
• ASE's founding role in the UCIe consortium reflects OSAT importance in turning chiplet standards into manufacturable system-in-package products.
• China is pursuing domestic advanced-packaging alternatives under technology-access constraints, while India's semiconductor activity is developing from a smaller packaging and assembly base.
• Brevintel analysis treats Asia Pacific as the critical volume-production geography for chiplet interconnect hardware.
• Asia Pacific's 35.91% CAGR exceeds North America's 34.48% because physical manufacturing capacity concentrates in the region.

Latin America and Middle East & Africa

• Latin America recorded USD 33.67 million in 2025 and is projected to reach USD 43.25 million in 2026, growing at a CAGR of 29.57%.
• Latin American revenue is primarily demand-led from imported data center, networking, consumer, and industrial systems containing chiplet-based processors.
• Brazil and Mexico offer the most plausible medium-term pathways for greater participation through electronics assembly and regional data-center demand.
• Middle East & Africa held USD 121.67 million in 2025 and is projected to reach USD 158.91 million in 2026, at a CAGR of 29.96%.
• MEA demand concentrates in AI infrastructure, cloud deployments, telecommunications, and high-performance computing imports rather than domestic chiplet manufacturing.
• Saudi Arabia and the UAE are the principal MEA demand centers because AI and data-center investment supports procurement of advanced accelerator hardware.
• Latin America and MEA, at 29.57% and 29.96% respectively, are more directly exposed to imported-system demand than to upstream component and package production.
• Brevintel analysis expects geopolitical concentration to sustain policy-driven North American packaging investment while Asian manufacturing remains decisive for AI-scale throughput.

Competitive Landscape

Market structure and share

• The market is moderately concentrated among vertically integrated processor, foundry, and packaging leaders.
• Intel held 18.2% of 2025 revenue, followed by AMD at 11.4%, NVIDIA at 10.7%, TSMC at 8.6%, and Samsung at 7.4%.
• Together, the five companies represented 56.3% of market revenue, with the remaining 43.7% distributed among IP licensors, EDA providers, OSAT companies, interface specialists, and emerging optical-interconnect suppliers.
• Intel combines advanced packaging platforms, processor products, and foundry ambitions, with EMIB and Foveros providing complementary horizontal and vertical chiplet routes including 45 µm EMIB bump pitch and 9 µm Foveros Direct copper bonding.
• AMD derives position from chiplet-based server processors and accelerator architectures using GMI3 links, and is a UCIe founding board member.
• NVIDIA participates through AI accelerator demand where package density, HBM integration, and high-bandwidth scale-up architectures make advanced interconnects commercially central.
• TSMC is strategically important because advanced packaging capacity converts fabless chiplet designs into volume hardware as a UCIe founding board member.
• Brevintel analysis expects competitive outcomes to hinge on qualified package capacity, interoperability proof points, and thermal co-design capability through 2035.

Recent developments

• UCIe 3.0 raised performance to 64 GT/s in August 2025, extending the open-standard roadmap beyond UCIe 2.0's 3D and manageability features.
• Ayar Labs' March 2025 announcement of an 8 Tbps UCIe-compliant optical I/O chiplet illustrates open electrical interfaces as entry points for optical technologies in AI scale-up architectures.
• U.S. Department of Commerce NAPMP funding of up to USD 1.6 billion and NIST USD 300 million advanced-packaging awards reinforce packaging as a policy priority.
• Intel's 2024 annual report identifies wafer fabrication, packaging, chiplets, and software and services as strategic components, with advanced packaging positioned as a foundry differentiator.
• Broadcom and Marvell bring high-speed connectivity and networking ASIC exposure where custom silicon requires dense compute, memory, and I/O integration.
• Cadence and Synopsys benefit from rising multi-die package planning, signal integrity, protocol validation, and 3D IC design burden.
• Alphawave Semi focuses on high-speed connectivity and die-to-die PHY IP for AI, HPC, and data-center applications.
• ASE and Amkor strengthen OSAT and advanced-packaging positions as interoperable chiplet designs move from specification into qualified system-in-package assembly.

Integrated producers

• Intel Corporation
• Advanced Micro Devices (AMD)
• NVIDIA Corporation
• Taiwan Semiconductor Manufacturing Company (TSMC)
• Samsung Electronics

IP, EDA, and interface specialists

• Broadcom Inc
• Marvell Technology
• Synopsys
• Cadence Design Systems
• Siemens EDA (Mentor Graphics)
• Alphawave Semi
• Ayar Labs
• Rambus

Advanced packaging and OSAT

• Amkor
• ASE